Design & Implementation of Fixed Width Modified Booth Multiplier Saroj

Multiplication is the main operation in many signal processing algorithms. High accuracy and low power dissipation are the most important objectives in many multimedia and lossy applications such as filtering, convolution, Euclidean distance, fast Fourier transform (FFT).The fixed width multipliers are used to maintain a fixed format and allow a little accuracy loss of output data. In this paper for the reduction of truncation errors modifies the partial product matrix and derive an error compensation function. A simple compensation circuit mainly composed of the simplified sorting network is also proposed. The proposed error compensation circuits offer reduction in mean square error over the previous circuits. Keyword: Fixed width multiplier, Error compensation circuit, Mean error, Mean square error, Modified booth multiplier